•   Phone: 962-031-5067   Email: jyothig@ssit.edu.in
    Designation : Assistant Professor
    Qualification : M Tech.,(Ph.D)
    Experience: 12 Years
    Birthdate: 06/07/1981
    Interests: Digital Electrinoics, VLSI
    Address: "Hari Nivas" I Floor, 5th cross,
      Saraswathipuram, Tumkur-572105
  • Qualifications

     Course  Specialization  Board / University  Year
     Pursuing Ph.D  VLSI  SSAHE  2014
     M.Tech  Electronics and Communication  IASE  2005
     B.Tech  Electronics and Instrumentation Engineering  JNTU-Hyderabad  2002


    A Survey on Synchronous and Asynchronous Counters using Reversible logic Gates
    Published on 31/10/2015
    at IJAREEIE - ISSN 2320-3765


    Design and Implementation of REA for Single Precision Floating Multiplier Using Reversible Logic
    Published on
    at IJAREEIE ISSN 2323-3765


    Design and implementation of Reversible Sequential Circuits
    Published on 22/10/2014
    at IJARCET ISSN 2278-1323


    Design Methodology for Single Precision Floating Point Multiplier Using Reversible Logic
    Published on
    at IJST


    Design of speed and power efficient 64*64 bit Urdhva multiplier
    Published on
    at IJIEEE


    “Introduction to Reversible Sequential Circuits”
    Published on 15/10/2015
    at National Conference on Emerging Treads in Electronics and communication (NCETEC-14), organized by BGSIT Mandya.